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LTC6802-2 Multicell Addressable Battery Stack Monitor FeaTures
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DescripTion
The LTC(R)6802-2 is a complete battery monitoring IC that includes a 12-bit ADC, a precision voltage reference, a high voltage input multiplexer and a serial interface. Each LTC6802-2 can measure 12 series connected battery cells, with a total input voltage up to 60V. The voltage on all 12 input channels can be measured within 13ms. Many LTC6802-2 devices can be stacked to measure the voltage of each cell in a long battery string. Each LTC6802-2 has an individually addressable serial interface, allowing up to 16 LTC6802-2 devices to interface to one control processor and operate simultaneously. To minimize power, the LTC6802-2 offers a measure mode to monitor each cell for overvoltage and undervoltage conditions. A standby mode is also provided to reduce supply current to 50A. Each cell input has an associated MOSFET switch that can discharge any overcharged cell. The related LTC6802-1 offers a serial interface that allows the serial ports of multiple LTC6802-1 devices to be daisy chained without opto-couplers or isolators.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
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Measures Up to 12 Li-Ion Cells in Series (60V Max) Stackable Architecture Enables Monitoring High Voltage Battery Stacks Individually Addressable with 4-Bit Address 0.25% Maximum Total Measurement Error 13ms to Measure All Cells in a System Cell Balancing: On-Chip Passive Cell Balancing Switches Provision for Off-Chip Passive Balancing Two Thermistor Inputs Plus Onboard Temperature Sensor 1MHz Serial Interface with Packet Error Checking High EMI Immunity Delta-Sigma Converter With Built-In Noise Filter Open-Wire Connection Fault Detection Low Power Modes 44-Lead SSOP Package
applicaTions
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Electric and Hybrid Electric Vehicles High Power Portable Equipment Backup Battery Systems High Voltage Data Acquisition Systems
Typical applicaTion
NEXT 12-CELL PACK ABOVE V+ LTC6802-2 DIE TEMP
MEASUREMENT ERROR (%) 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -50
68022 TA01a
Measurement Error Over Extended Temperature
7 REPRESENTATIVE UNITS VS = 43.2V CELL VOLTAGE 3.6V
+
SERIAL DATA REGISTERS AND CONTROL MUX 4-BIT ADDRESS
12-CELL BATTERY STRING
+ +
V
-
12-BIT ADC
NEXT 12-CELL PACK BELOW 100k NTC
EXTERNAL TEMP
VOLTAGE REFERENCE
-25
0 25 50 75 TEMPERATURE (C)
100
125
68022 TA01b
100k
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LTC6802-2 absoluTe MaxiMuM raTings
(Note 1)
pin conFiguraTion
TOP VIEW V+ C12 S12 C11 S11 C10 S10 C9 S9 1 2 3 4 5 6 7 8 9 44 CSBI 43 SDO 42 SDI 41 SCKI 40 A3 39 A2 38 A1 37 A0 36 GPIO2 35 GPIO1 34 WDTB 33 MMB 32 TOS 31 VREG 30 VREF 29 VTEMP2 28 VTEMP1 27 NC 26 V- 25 S1 24 C1 23 S2
Total Supply Voltage (V+ to V-) .................................60V Input Voltage (Relative to V-) C1 ............................................................ -0.3V to 9V C12 ..........................................V+ - 0.6V to V+ + 0.3V Cn (Note 5) ......................... -0.3V to Min (9 * n, 60V) Sn (Note 5) ......................... -0.3V to Min (9 * n, 60V) All Other Pins ........................................... -0.3V to 7V Voltage Between Inputs Cn to Cn - 1 ............................................. -0.3V to 9V Sn to Cn - 1 ............................................. -0.3V to 9V C12 to C8 ............................................... -0.3V to 25V C8 to C4 ................................................. -0.3V to 25V C4 to V- ................................................. -0.3V to 25V Operating Temperature Range.................. -40C to 85C Specified Temperature Range .................. -40C to 85C Junction Temperature ........................................... 150C Storage Temperature Range................... -65C to 150C *n = 1 to 12
C8 10 S8 11 C7 12 S7 13 C6 14 S6 15 C5 16 S5 17 C4 18 S4 19 C3 20 S3 21 C2 22
G PACKAGE 44-LEAD PLASTIC SSOP TJMAX = 150C, JA = 70C/W
orDer inForMaTion
LEAD FREE FINISH LTC6802IG-2#PBF TAPE AND REEL LTC6802IG-2#TRPBF PART MARKING LTC6802G-2 PACKAGE DESCRIPTION 44-Lead Plastic SSOP TEMPERATURE RANGE -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC6802-2 elecTrical characTerisTics
SYMBOL PARAMETER DC Specifications VACC Measurement Resolution ADC Offset Voltage ADC Gain Error VERR Total Measurement Error Quantization of the ADC (Note 2) (Note 2)
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+ = 43.2V, V- = 0V, unless otherwise noted.
CONDITIONS MIN TYP 1.5 -0.5 -0.12 -0.22 0.8 0.5 0.12 0.22 MAX UNITS mV/Bit mV % % mV mV mV mV mV mV mV mV mV mV mV V 5*n 15 10 5 4.200 2.300 3
l
(Note 4) VCELL = 0V VCELL = 2.3V VCELL = 2.3V VCELL = 3.6V VCELL = 3.6V VCELL = 4.2V VCELL = 4.2V VCELL = 4.6V VTEMP = 2.3V VTEMP = 3.6V VTEMP = 4.2V Full-Scale Voltage Range
l l l l l l
-2.8 -5.1 -4.3 -7.9 -5 -9.2 -5.1 -7.9 -9.2 3.7 1.8 1.2 0 4.182 2.290 3.020 3.015
8
2.8 5.1 4.3 7.9 5 9.2 5.1 7.9 9.2
VCELL VCM
Cell Voltage Range
5
l l l l l l
Common Mode Voltage Range Measured Range of Inputs Cn for <0.25% Gain Error, n = 3 to 11 Relative to V- Range of Input C3 for <1% Gain Error Range of Input C2 for <0.25% Gain Error Range of Input C1 for <0.25% Gain Error Overvoltage (OV) Detection Level Undervoltage (UV) Detection Level Die Temperature Measurement Error Programmed for 4.2V Programmed for 2.3V Error in Measurement at 125C RLOAD = 100k to V-
V V V V V V C V V ppm/C ppm ppm/kHr
4.218 2.310 3.110 3.115
VREF
Reference Pin Voltage Reference Voltage Temperature Coefficient Reference Voltage Thermal Hysteresis Reference Voltage Long-Term Drift
3.065 3.065 8
25C to 85C and 25C to -40C 10 < V+ < 50, No Load ILOAD = 4mA VERR Specifications Met Timing Specifications Met In/Out of Pins C1 Through C12 When Measuring Cells When Not Measuring Cells
l l l l l l
100 60 4.5 4.1 5 10 4 -10 5.0 4.8 8 50 50 10 1.1 1.2 5.5
VREG
Regulator Pin Voltage Regulator Pin Short-Circuit Current Limit
V V mA V V A nA mA mA
VS IB IS IM
Supply Voltage, V+ Relative to V- Input Bias Current
1 0.8
Supply Current, Active Supply Current, Monitor Mode
Current Into the V+ Pin When Measuring Voltages with l the ADC Average Current Into the V+ Pin While Monitoring for UV and OV Conditions Continuous Monitoring (CDC = 2) Monitor Every 130ms (CDC = 5) Monitor Every 500ms (CDC = 6) Monitor Every 2 Seconds (CDC = 7) Current Into the V+ Pin When Idle All Serial Port Pins at Logic `1'
l
800 225 150 100 37.5 32.5 62.5 82.5 87.5
A A A A A A
IQS
Supply Current, Idle
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LTC6802-2 elecTrical characTerisTics
SYMBOL PARAMETER Discharge Switch On-Resistance Temperature Range Thermal Shutdown Temperature Thermal Shutdown Hysteresis Timing Specifications tCYCLE t1 t2 t3 t4 t5 t6 t7 t8 Measurement Cycle Time Time Required to Measure 11 or 12 Cells Time Required to Measure Up to 10 Cells Time Required to Measure 1 Cell
l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+ = 43.2V, V- = 0V, unless otherwise noted.
CONDITIONS VCELL > 3V (Note 3)
l l
MIN -40
TYP 10 145 5
MAX 20 85
UNITS C C C
11 9.2 1 10 250 400 400 400 100 100
13 11 1.2
16 13.5 1.5
ms ms ms ns ns ns ns ns ns ns
SDI Valid to SCKI Rising Setup SDI Valid to SCKI Rising Hold SCKI Low SCKI High CSBI Pulse Width SCKI Rising to CSBI Rising CSBI Falling to SCKI Rising SCKI Falling to SDO Valid Clock Frequency Watchdog Timer Time-Out Period
250 1 1 2 0.8 0.3 2.5
ns MHz s V V V
Digital I/O Specifications VIH VIL VOL Digital Voltage Input High Digital Voltage Input Low Digital Voltage Output Low Sinking 500A
l l l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The ADC specifications are guaranteed by the total measurement error (VERR) specification. Note 3: Due to the contact resistance of the production tester, this specification is tested to relaxed limits. The 20 limit is guaranteed by design.
Note 4: VCELL refers to the voltage applied across the following pin combinations: Cn to Cn - 1 for n = 2 to 12, C1 to V-. VTEMP refers to the voltage applied from VTEMP1 or VTEMP2 to V- Note 5: These absolute maximum ratings apply provided that the voltage between inputs do not exceed their absolute maximum ratings.
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LTC6802-2 Typical perForMance characTerisTics
Cell Measurement Total Unadjusted Error
10 TOTAL UNADJUSTED ERROR (mV) 8 6 4 2 0 -2 -4 -6 -8 -10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL VOLTAGE (V)
68022 G09
Cell Measurement Total Unadjusted Error vs Input Resistance
10 TOTAL UNADJUSTED ERROR (mV) 0 -10 -20 -30 -40 -50 RS = 1k RS = 2k RS = 5k RS = 10k -60 RS IN SERIES WITH Cn AND Cn - 1 -70 NO EXTERNAL CAPACITANCE ON Cn AND Cn - 1 -80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL VOLTAGE (V)
68022 G10
Measurement Gain Error Hysteresis
25 TA = 85C TO 25C
TA = -40C TA = 25C TA = 85C TA = 125C
20 NUMBER OF UNITS
15
10
5
0 -250 -200 -150 -100 -50 0 50 100 150 200 CHANGE IN GAIN ERROR (ppm)
68022 G20
Measurement Gain Error Hysteresis
20 18 16 NUMBER OF UNITS REJECTION (db) 14 12 10 8 6 4 2 0 -250 -200 -150 -100 -50 0 50 100 150 200 CHANGE IN GAIN ERROR (ppm)
68022 G21
Cell Measurement Common Mode Rejection
VCM(IN) = 5VP-P 72dB REJECTION -10 CORRESPONDS TO LESS THAN 1 BIT -20 AT ADC OUTPUT -30 -40 -50 -60 -70 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M
68022 G15
ADC Normal Mode Rejection vs Frequency
0 -10 -20 REJECTION (db) -30 -40 -50 -60 -70 10 100 1k 10k FREQUENCY (Hz) 100k
68022 G14
TA = -45C TO 25C
0
ADC INL
2.0 1.5 1.0 DNL (BITS) INL (BITS) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 1 2 3 INPUT (V) 4 5
68022 G05
ADC DNL
1.0 0.8 C PIN BIAS CURRENT (nA) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 3 2 INPUT (V) 4 5
68022 G06
Cell Input Bias Current in Standby
50 40 30 20 C12 10 0 C2 TO C11 -10 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120
68022 G03
C1
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LTC6802-2 Typical perForMance characTerisTics
Cell Input Bias Current During Conversion
2.70 2.65 C PIN BIAS CURRENT (A) 2.60 2.55 2.50 2.45 2.40 2.35 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120
68022 G04
Supply Current vs Supply Voltage Standby
60 STANDBY SUPPLY CURRENT (A) 50 SUPPLY CURRENT (mA) 40 30 20 10 0 TA = -40C TA = 25C TA = 85C 0 10 20 30 40 SUPPLY VOLTAGE (V) 50 60
68022 G01
Supply Current vs Supply Voltage in CDC = 2
0.90 0.85 0.80 0.75 0.70 0.65 0.60 CDC = 2 (CONTINUOUS CELL CONVERSIONS) TA = 85C TA = 25C TA = -40C
CELL INPUT = 3.6V
0
10
20 30 40 SUPPLY VOLTAGE (V)
50
60
68022 G02
DIFFERENCE BETWEEN INTERNAL DIE TEMPERATURE MEASUREMENT AND AMBIENT TEMPERATURE (C)
Internal Die Temperature Measurement vs Ambient Temperature
5 4 3 2 1 0 -1 -2 -3 -4 -5 -50 DEVICE IN STANDBY PRIOR TO MAKING DIE MEASUREMENTS TO MINIMIZE SELF HEATING -25 0 25 50 75 100 AMBIENT TEMPERATURE (C) 125 VS = 43.2V TOTAL UNADJUSTED ERROR (mV) 10 5 0 -5 -10 -15 -20
External Temperature Measurement Total Unadjusted Error vs Input
3.070 3.068 3.066 VREF (V) 3.064 3.062 3.060 3.058
VREF Output Voltage vs Temperature
TA = -40C TA = 25C TA = 85C TA = 105C 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE INPUT VOLTAGE (V)
68022 G13
5 REPRESENTATIVE UNITS 3.056 -50 -25 25 75 0 50 TEMPERATURE (C)
100
125
68022 G12
68022 G22
3.09
VREF Load Regulation
3.074 3.072 3.070
VREF Line Regulation
NO EXTERNAL LOAD ON VREF, CDC = 2 (CONTINUOUS CELL CONVERSIONS)
5.4 5.2 5.0 VREG (V)
VREG Load Regulation
3.08
TA = 85C TA = 25C TA = -40C
VREF (V)
VREF (V)
3.07
3.068 3.066 3.064
TA = 25C TA = 85C TA = -40C
4.8 4.6 4.4 4.2
3.06
3.05
3.04
TA = -40C TA = 25C TA = 85C 0 10 100 SOURCING CURRENT (A) 1000
68022 G07
3.062 3.060 0 10 20 30 40 SUPPLY VOLTAGE (V) 50 60
68022 G08
4.0
0
1
2
345678 SUPPLY CURRENT (mA)
9
10
68022 G16
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LTC6802-2 Typical perForMance characTerisTics
5.5
VREG Line Regulation
TA = 85C
Internal Discharge Resistance vs Cell Voltage
50 45 DISCHARGE RESISTANCE ( ) 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CELL VOLTAGE (V)
68022 G11
5.0
TA = -45C TA = 25C TA = 85C TA = 105C
VREG (V)
4.5 TA = 25C 4.0
TA = -40C
3.5 NO EXTERNAL LOAD ON VREG, CDC = 2 (CONTINUOUS CELL CONVERSIONS) 5 15 25 35 45 SUPPLY VOLTAGE (V) 55
68022 G17
3.0
Die Temperature Increase vs Discharge Current in Internal FET
50 INCREASE IN DIE TEMPERATURE (C) ALL 12 CELLS AT 3.6V 45 VS = 43.2V TA = 25C 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 DISCHARGE CURRENT PER CELL (mA)
68022 G18
Cell Conversion Time
13.20 13.15 CONVERSION TIME (ms) 13.10 13.05 13.00 12.95 12.90 12.85 12.80 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120
68022 G19
12 CELLS DISCHARGING
6 CELLS DISCHARGING 1 CELL DISCHARGING
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LTC6802-2 pin FuncTions
V+ (Pin 1): Tie Pin 1 to the most positive potential in the battery stack. V+ must be approximately the same potential as C12. C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1 through C12 are the inputs for monitoring battery cell voltages. Up to 12 cells can be monitored. The lowest potential is tied to the V- pin. The next lowest potential is tied to C1 and so forth. See the figures in the Applications Information section for more details on connecting batteries to the LTC6802-2. S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though S12 pins are used to balance battery cells. If one cell in a series becomes over charged, an S output can be used to discharge the cell. Each S output is an internal N-channel MOSFET for discharging. See the Block Diagram. The NMOS has a maximum on-resistance of 20. An external resistor should be connected in series with the NMOS to dissipate heat outside of the LTC6802-2 package. When using the internal MOSFETs to discharge cells, the die temperature should be monitored. See Power Dissipation and Thermal Shutdown in the Applications Information section. The S pins also feature an internal 10k pull-up resistor. This allows the S pins to be used to drive the gates of external P-channel MOSFETs for higher discharge capability. V- (Pin 26): Connect V- to the most negative potential in the series of cells. NC (Pin 27): Pin 27 is internally connected to V- through 10. Pin 27 can be left unconnected or connect Pin 27 to Pin 26 on the PCB. VTEMP1, VTEMP2 (Pins 28, 29): Temperature Sensor Inputs. The ADC will measure the voltage on VTEMPx with respect to V- and store the result in the TMP register. The ADC measurements are relative to the VREF pin voltage. Therefore a simple thermistor and resistor combination connected to the VREF pin can be used to monitor temperature. The VTEMP inputs can also be general purpose ADC inputs. VREF (Pin 30): 3.075V Voltage Reference Output. This pin should be bypassed with a 1F capacitor. The VREF pin can drive a 100k resistive load connected to V-. Larger loads should be buffered with an LT6003 op amp, or similar device. VREG (Pin 31): Linear Voltage Regulator Output. This pin should be bypassed with a 1F capacitor. The VREG is capable of sourcing up to 4mA to an external load. The VREG pin does not sink current. TOS (Pin 32): Top of Stack Input. The TOS pin can be tied to VREG or V- for the LTC6802-2. The state of the TOS pin alters the operation of the SDO pin in the toggle polling mode. See the Serial Port description. MMB (Pin 33): Monitor Mode Input (Active Low). When MMB is low (same potential as V-), the LTC6802-2 goes into monitor mode. See Modes of Operation in the Applications Information section. WDTB (Pin 34): Watchdog Timer Output (Active Low). If there is no activity on the SCKI pin for 2.5 seconds, the WDTB output is asserted. The WDTB pin is an open-drain NMOS output. When asserted it pulls the output down to V- and resets the configuration register to its default state. See Watchdog Timer Circuit in the Applications Information section. GPIO1, GPIO2 (Pins 35, 36): General Purpose Input/Output. The operation of these pins depends on the state of the MMB pin. When MMB is high, the pins behave as traditional GPIOs. By writing a "0" to a GPIO configuration register bit, the open drain output is activated and the pin is pulled to V-. By writing a logic "1" to the configuration register bit, the corresponding GPIO pin is high impedance. An external resistor is needed to pull the pin up to VREG. By reading the configuration register locations GPIO1 and GPIO2, the state of the pins can be determined. For example, if a "0" is written to register bit GPIO1, a "0" is always read back because the output NMOSFET pulls Pin 35 to V-. If a "1" is written to register bit GPIO1, the
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LTC6802-2 pin FuncTions
pin becomes high impedance. Either a "1" or a "0" is read back, depending on the voltage present at Pin 35. The GPIOs make it possible to turn on/off circuitry around the LTC6802-2, or read logic values from a circuit around the LTC6802-2. When the MMB pin is low, the GPIO pins and the WDTB pin are treated as inputs that set the number of cells to be monitored. See Monitor Mode in the Applications Information section. A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs. These pins are tied to VREG or V-. The state of the address pins (VREG = 1, V- = 0) determines the LTC6802-2 address. See LTC6802-2 Address Commands in the Serial Port subsection of the Applications Information section. SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces to any logic gate (TTL levels). See Serial Port in the Applications Information section. SDI (Pin 42): Serial Data Input. The SDI pin interfaces to any logic gate (TTL levels). See Serial Port in the Applications Information section. SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS open drain output and requires an external resistor pull-up. See Serial Port in the Applications Information section. CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI pin interfaces to any logic gate (TTL levels). See Serial Port in the Applications Information section.
block DiagraM
1 V+ 2 C12 10k 3 S12 WATCHDOG TIMER C11 A3 A2 10k 21 S3 MUX 22 C2 10k 23 S2 A/D CONVERTER 12 RESULTS REGISTER AND COMMUNICATIONS A1 A0 CSBI SDO SDI SCKI 40 39 38 37 44 43 42 41 WDTB 34 REGULATOR VREG 31
4
24
C1 10k REFERENCE GPIO2 GPIO1 CONTROL V- 10 MMB TOS 36 35 33 32
25
S1
26
27
NC
DIE TEMP VTEMP1 28
EXTERNAL TEMP VTEMP2 29 VREF 30
68022 BD
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LTC6802-2 TiMing DiagraM
Timing Diagram of the Serial Interface
t1 t2 SCKI t4 t3 t6 t7
SDI
D3
D2
D1
D0
D7 ... D4
D3
t5 CSBI t8 SDO D4 PREVIOUS COMMAND D3 D2 D1 D0 D7 ... D4 CURRENT COMMAND D3
68022 TD
operaTion
THEORY OF OPERATION The LTC6802-2 is a data acquisition IC capable of measuring the voltage of 12 series connected battery cells. An input multiplexer connects the batteries to a 12-bit delta-sigma analog to digital converter (ADC). An internal 5ppm voltage reference combined with the ADC give the LTC6802-2 its outstanding measurement accuracy. The inherent benefits of the delta-sigma ADC vs other types of ADCs (e.g. successive approximation) are explained in Advantages of Delta-Sigma ADCs in the Applications Information section. Communication between the LTC6802-2 and a host processor is handled by a SPI compatible serial interface. Multiple LTC6802-2s can be connected to a single serial interface. This is shown in Figure 1. The LTC6802-2s are isolated from one another using digital isolators. A unique addressing scheme allows all LTC6802-2s to connect to the same serial port of the host processor. Further explanation of the LTC6802-2 can be found in the Serial Port section of the data sheet. The LTC6802-2 also contains circuitry to balance cell voltages. Internal MOSFETs can be used to discharge cells. These internal MOSFETs can also be used to control external balancing circuits. Figure 1 illustrates cell balancing by internal discharge. Figure 4 shows the S pin controlling an external balancing circuit. It is important to note that the LTC6802-2 makes no decisions about turning on/off the internal MOSFETs. This is completely controlled by the host processor. The host processor writes values to a configuration register inside the LTC6802-2 to control the switches. The watchdog timer on the LTC6802-2 can be used to turn off the discharge switches if communication with the host processor is interrupted. OPEN-CONNECTION DETECTION When a cell input (C pin) is open, it affects 2-cell measurements. Figure 2 shows an open connection to C3, in an application without external filtering between the C pins and the cells. During normal ADC conversions (that is, using the STCVAD command), the LTC6802 will give near zero readings for B3 and B4 when C3 is open. The zero reading for B3 occurs because during the measurement of B3, the ADC input resistance will pull C3 to the C2 potential. Similarly, during the measurement of B4, the ADC input resistance pulls C3 to the C4 potential. Figure 3 shows an open connection at the same point in the cell stack as Figure 2, but this time there is an external filter network still connected to C3. Depending on the value of the capacitor remaining on C3, a normal measurement of B3 and B4 may not give near zero readings, since the C3 pin is not truly open. In fact, with a large external capacitance on C3, the C3 voltage will be charged midway
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0
LTC6802-2 operaTion
IC #3 TO IC #7 V2- OE2 V1- OE1 BATTERY POSITIVE 350V V2- OE2 V1- OE1
+ + + + + + + + + + + +
LTC6802-2 IC #2 V+ CSBI C12 SDO S12 SDI C11 SCKI S11 A3 C10 A2 S10 A1 C9 A0 S9 GPIO2 C8 GPIO1 S8 WDTB C7 MMB S7 TOS C6 VREG VREF S6 VTEMP2 C5 VTEMP1 S5 NC C4 V- S4 S1 C3 C1 S3 S2 C2
+
ADDRESS 1 V2- V1- V2+ V1+ DIGITAL ISOLATOR
+
3V
+ + + + + + + + + +
LTC6802-2 IC #8 V+ CSBI C12 SDO S12 SDI C11 SCKI S11 A3 C10 A2 S10 A1 C9 A0 S9 GPIO2 C8 GPIO1 S8 WDTB C7 MMB S7 TOS C6 VREG VREF S6 VTEMP2 C5 VTEMP1 S5 NC C4 V- S4 S1 C3 C1 S3 S2 C2
ADDRESS 15
V2- V1- V2+ V1+ DIGITAL ISOLATOR
3V
+ + + + + + + + + + + +
LTC6802-2 IC #1 V+ CSBI C12 SDO S12 SDI C11 SCKI S11 A3 C10 A2 S10 A1 C9 A0 S9 GPIO2 C8 GPIO1 S8 WDTB C7 MMB S7 TOS C6 VREG VREF S6 VTEMP2 C5 VTEMP1 S5 NC C4 V- S4 S1 C3 C1 S3 S2 C2
V2- OE2
V1- OE1 MISO CS MOSI CLK 3V
3V MPU MODULE IO
ADDRESS 0
V2- V1- V2+ V1+ DIGITAL ISOLATOR
68022 F01
Figure 1. 96-Cell Battery Stack, Isolated Interface. In this Diagram the Battery Negative is Isolated from Module Ground. Opto-Couplers or Digital Isolators Allow Each IC to be Addressed Individually. This is a Simplified Schematic Showing the Basic Multi-IC Architecture
between C2 and C4 after several cycles of measuring cells B3 and B4. Thus the measurements for B3 and B4 may indicate a valid cell voltage when in fact the exact state of B3 and B4 is unknown. To reliably detect an open connection, the command STOWAD is provided. With this command, two 100A current sources are connected to the ADC inputs and
turned on during all cell conversions. Referring again to Figure 3, with the STOWAD command, the C3 pin will be pulled down by the 100A current source during the B3 cell measurement AND during the B4 cell measurement. This will tend to decrease the B3 measurement result and increase the B4 measurement result relative to the normal STCVAD command. The biggest change is observed in the
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LTC6802-2 operaTion
LTC6802-2
4. Issue a RDCV command and store all cell measurements into array CELLB(n). 5. For each value of n from 1 to 11: If CELLB(n + 1) - CELLA(n + 1) +200mV,
B4 B3
+ + + +
C4 C3 C2 C1 V- MUX
then Cn is open, otherwise it is not open. The 200mV threshold is chosen to provide tolerance for errors in the measurement with the 100A current source connected. Even without an open connection there is always some difference between a cell measured with and without the 100A current source because of the IR drop across the finite resistance of the MUX switches. On the other hand, with capacitors larger then 0.1F remaining on an otherwise open C pin, the 100A current source may not be enough to move the open C pin 200mV with a single STOWAD command. If the STOWAD command is repeated several times, the large external capacitor will discharge enough to create a 200mV change in cell readings. To detect an open connection with larger then 0.1F capacitance still on the pin, one must repeat step 3 a number of times before proceeding to step 4. The algorithm above determines if the Cn pin is open based on measurements of the n + 1 cell. For example, in a 12-cell system, the algorithm finds opens on Pins C1 through C11 by looking at the measurements of cells B2 through B12. Therefore the algorithm can not be used to determine if the topmost C pin is open. Fortunately, an open wire from the battery to the top C pin usually means the V+ pin is also floating. When this happens, the readings for the top battery cell will always be 0V, indicating a failure. If the top C pin is open yet V+ is still connected, then the best way to detect an open connection to the top C pin is by comparing the sum of all cell measurements using the STCVAD command to an auxiliary measurement of the sum of all the cells, using a method similar to that shown in Figure 15. A significantly lower result for the calculated sum of all 12 cells suggests an open connection to the top C pin, provided it was already determined that no other C pin is open.
100A
68022 F02
Figure 2. Open Connection
LTC6802-2
+
B4 B3
+ + + +
C4 CF4 CF3 C3 C2 C1 V- MUX
100A
68022 F03
Figure 3. Open Connection with RC Filtering
B4 measurement when C3 is open. So, the best method to detect an open wire at input C3 is to look for an increase in the measurement of the cell connected between inputs C3 and C4 (cell B4). Thus the following algorithm can be used to detect an open connection to cell pin Cn: 1. Issue a STCVAD command (ADC convert without 100A current sources). 2. Issue a RDCV command and store all cell measurements into array CELLA(n). 3. Issue a STOWAD command (ADC convert with 100A current sources).
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DISCHARGING DURING CELL MEASUREMENTS The primary cell voltage A/D measurement commands (STCVAD and STOWAD) automatically turn off a cell's discharge switch while its voltage is being measured. The discharge switches for the cell above and the cell below will also be turned off during the measurement. For example, discharge switches S4, S5, and S6 will be disabled while cell 5 is being measured. In some systems it may be desirable to allow discharging to continue during cell voltage measurements. The cell voltage A/D conversion commands STCVDC and STOWDC allow any enabled discharge switches to remain on during cell voltage measurements. This feature allows the system to perform a self test to verify the discharge functionality and multiplexer operation. All discharge switches are automatically disabled during OV and UV comparison measurements. A/D CONVERTER DIGITAL SELF TEST Two self-test commands can be used to verify the functionality of the digital portions of the ADC. The self tests also verify the cell voltage registers and cell temperature registers. During these self tests a test signal is applied to the ADC. If the circuitry is working properly the cell voltage or cell temperature registers will contain identical codes. For self test 1 the registers will contain 0x555. For self test 2, the registers will contain 0xAAA. The time required for the self-test function is the same as required to measure all cell voltages or all temperature sensors. Perform the self-test function with CDC[2:0] set to 1 in the configuration register. USING THE S PINS AS DIGITAL OUTPUTS OR GATE DRIVERS The S outputs include an internal 10k pull-up resistor. Therefore the S pins will behave as a digital output when loaded with a high impedance, e.g., the gate of an external MOSFET. For applications requiring high battery discharge currents, connect a discrete PMOS switch device and suitable discharge resistor to the cell, and the gate terminal to the S output pin, as illustrated in Figure 4.
SI2351DS Cn MM3Z12VT1 3.3k 15 1W VISHAY CRCW2512 SERIES
68022 F04
+
Sn Cn - 1
Figure 4. External Discharge FET Connection (One Cell Shown)
POWER DISSIPATION AND THERMAL SHUTDOWN The MOSFETs connected to the Pins S1 through S12 can be used to discharge battery cells. An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6802-2. Excessive heat results in elevated die temperatures. The electrical characteristics are guaranteed for die temperatures up to 85C. Little or no degradation will be observed in the measurement accuracy for die temperatures up to 105C. Damage may occur near 150C, therefore the recommended maximum die temperature is 125C. To protect the LTC6802-2 from damage due to overheating, a thermal shutdown circuit is included. Overheating of the device can occur when dissipating significant power in the cell discharge switches. The problem is exacerbated when operating with a large voltage between V+ and V- or when the thermal conductivity of the system is poor. If the temperature detected on the device goes above approximately 145C, the configuration registers will be reset to default states, turning off all discharge switches and disabling A/D conversions. When a thermal shutdown has occurred, the THSD bit in the temperature register group will go high. The bit is cleared by performing a read of the temperature registers (RDTMP command). Since thermal shutdown interrupts normal operation, the internal temperature monitor should be used to determine when the device temperature is approaching unacceptable levels.
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USING THE LTC6802-2 WITH LESS THAN 12 CELLS The LTC6802-2 can typically be used with as few as 4 cells. The minimum number of cells is governed by the supply voltage requirements of the LTC6802-2. The sum of the cell voltages must be 10V to guarantee that all electrical specifications are met. Figure 5 shows an example of the LTC6802-2 when used to monitor 7 cells. The lowest C inputs connect to the 7 cells and the upper C inputs connect to V+. Other configurations, e.g., 9 cells, would be configured in the same way: the lowest C inputs connected to the battery cells and the unused C inputs connected to V+. The unused inputs will result in a reading of 0V for those channels. The ADC can also be commanded to measure a stack of cells by making 10 or 12 measurements, depending on the state of the CELL10 bit in the control register. Data from all 10 or 12 measurements must be downloaded when reading the conversion results. The ADC can be commanded to measure any individual cell voltage.
NEXT HIGHER GROUP OF 7 CELLS V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 V- LTC6802-2
USING THE GENERAL PURPOSE INPUTS/OUTPUTS (GPIO1, GPIO2) The LTC6802-2 has two general purpose digital inputs/outputs. By writing a GPIO configuration register bit to a logic low, the open-drain output can be activated. The GPIOs give the user the ability to turn on/off circuitry around the LTC6802-2. One example might be a circuit to verify the operation of the system. When a GPIO configuration bit is written to a logic high, the corresponding GPIO pin may be used as an input. The read back value of that bit will be the logic level that appears at the GPIO pin. When the MMB pin is low, the GPIO pins and the WDTB pin are treated as inputs that set the number of cells to be monitored. See the Monitor Mode section. WATCHDOG TIMER CIRCUIT The LTC6802-2 includes a watchdog timer circuit. If no activity is detected on the SCKI pin for 2.5 seconds, the WDTB open-drain output is asserted low. The WDTB pin remains low until an edge is detected on the SCKI pin. When the watchdog timer circuit times out, the configuration bits are reset to their default (power-up) state. In the power-up state, the S outputs are off. Therefore, the watchdog timer provides a means to turn off cell discharging should communications to the MPU be interrupted. The IC is in the minimum power standby mode after a time out. Note that externally pulling the WDTB pin low will not reset the configuration bits. The watchdog timer operation is disabled when MMB is low. When reading the configuration register, byte CFG0 bit 7 will reflect the state of the WDTB pin. REVISION CODE The temperature register group contains a 3-bit revision code. If software detection of device revision is necessary, then contact the factory for details. Otherwise, the code can be ignored. In all cases, however, the values of all bits must be used when calculating the packet error code (PEC) CRC byte on data reads.
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+ + + + + + +
NEXT LOWER GROUP OF 7 CELLS
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Figure 5. Monitoring 7 Cells with the LTC6802-2
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MODES OF OPERATION The LTC6802-2 has three modes of operation: standby, measure and monitor. Standby mode is a power saving state where all circuits except the serial interface are turned off. In measure mode, the LTC6802-2 is used to measure cell voltages and store the results in memory. Measure mode will also monitor each cell voltage for overvoltage (OV) and undervoltage (UV) conditions. In monitor mode, the device will only monitor cells for UV and OV conditions. A signal is output on the SDO pin to indicate the UV/OV status. The serial interface is disabled. Standby Mode The LTC6802-2 defaults (powers up) to standby mode. Standby mode is the lowest possible supply current state. All circuits are turned off except the serial interface and the voltage regulator. The LTC6802-2 can be programmed for standby mode by setting configuration bits CDC[2:0] to 0. If the part is put into standby mode while ADC measurements are in progress, the measurements will be interrupted and the cell voltage registers will be in an indeterminate state. To exit standby mode, the CDC bits must be written to a value other than 0. Measure Mode The LTC6802-2 is in measure mode when the CDC bits are programmed with a value from 1 to 7. The IC monitors each cell voltage and produces an interrupt signal on the SDO pin indicating all cell voltages are within the UV and OV limits. There are two methods for indicating the UV/OV interrupt status: toggle polling (using a 1kHz output signal) and level polling (using a high or low output signal). The polling methods are described in the Serial Port section. The UV/OV limits are set by the VUV and VOV values in the configuration registers. When a cell voltage exceeds the UV/OV limits a bit is set in the flag register. The UV and OV flag status for each cell can be determined using the Read Flag Register Group. If fewer than 12 cells are connected to the LTC6802-2 then it is necessary to mask the unused input channels. The MCxI bits in the configuration registers are used to mask channels. If the CELL10 bit is high, then the inputs for cells 11 and 12 are automatically masked. The LTC6802-2 can monitor UV and OV conditions continuously. Alternatively, the duty cycle of the UV and OV comparisons can be reduced or turned off to lower the overall power consumption. The CDC bits are used to control the duty cycle. To initiate cell voltage measurements while in measure mode, a Start A/D Conversion and Poll Status command must be sent. After the command has been sent, the LTC6802-2 will send the A/D converter status using either the toggle polling or the level polling method, as described in the Serial Port section. If the CELL10 bit is high, then only the bottom 10 cell voltages will be measured, thereby reducing power consumption and measurement time. By default the CELL10 bit is low, enabling measurement of all 12 cell voltages. During cell voltage measurement commands, UV and OV flag conditions, reflected in the flag register group, are also updated. When the measurements are complete, the part will go back to monitoring UV and OV conditions at the rate designated by the CDC bits. Monitor Mode The LTC6802-2 can be used as a simple monitoring circuit with no serial interface by pulling the MMB pin low. When in this mode, the interrupt status is indicated on the SDO pin using the toggle polling mode described in the Serial Port section. Unlike serial port polling commands, however, the toggling is independent of the state of the CSBI pin. When the MMB pin is low, all the device configuration values are reset to the default states shown in Table 15 Memory Bit Descriptions. When MMB is held low the VUV, VOV, and CDC register values are ignored. Instead VUV and VOV use factory-programmed setings. CDC is set to state 5. The number of cells to be monitored is set by the logic levels on the WDTB and GPIO pins, as shown in Table 1.
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Table 1. Monitor Mode Cell Selection
WDTB 0 0 0 0 1 1 1 1 GPIO2 0 0 1 1 0 0 1 1 GPIO1 0 1 0 1 0 1 0 1 CELL INPUTS MONITORED Cells 1 to 5 Cells 1 to 6 Cells 1 to 7 Cells 1 to 8 Cells 1 to 9 Cells 1 to 10 Cells 1 to 11 Cells 1 to 12
(logic high) for polling commands. All interface pins are voltage mode, with voltage levels sensed with respect to the V- supply. See Figure 1. Data Link Layer Clock Phase And Polarity: The LTC6802-2 SPI compatible interface is configured to operate in a system using CPHA = 1 and CPOL = 1. Consequently, data on SDI must be stable during the rising edge of SCKI. Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. On a write, the data value on SDI is latched into the device on the rising edge of SCKI (Figure 6). Similarly, on a read, the data value output on SDO is valid during the rising edge of SCKI and transitions on the falling edge of SCKI (Figure 7). CSBI must remain low for the entire duration of a command sequence, including between a command byte and subsequent data. On a write command, data is latched in on the rising edge of CSBI. After a polling command has been entered, the SDO output will immediately be driven by the polling state, with the SCKI input ignored (Figure 8). See the Toggle Polling and Level Polling sections. Network Layer Broadcast Commands: A broadcast command is one to which all devices on the bus will respond, regardless of device address. See the Bus Protocols and Commands sections.
If MMB is low then brought high, all device configuration values are reset to the default states including the VUV, VOV, and CDC configuration bits. SERIAL PORT Overview The LTC6802-2 has an SPI bus compatible serial port. Devices can be connected in parallel, using digital isolators. Multiple devices are uniquely identified by a part address determined by the A0 to A3 pins. Physical Layer On the LTC6802-2, four pins comprise the serial interface: CSBI, SCKI, SDI and SDO. The SDO and SDI may be tied together, if desired, to form a single, bidirectional port. Four address pins (A0 to A3) set the part address for address commands. The TOS pin designates the top device
CSBI
SCKI
SDI
MSB (CMD)
BIT6 (CMD)
LSB (CMD)
MSB (DATA)
LSB (DATA)
68022 F06
Figure 6. Transmission Format (Write)
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CSBI
SCKI
SDI
MSB (CMD)
BIT6 (CMD)
LSB (CMD)
SDO
MSB (DATA)
LSB (DATA)
68022 F07
Figure 7. Transmission Format (Read)
CSBI
SCKI
SDI
MSB (CMD)
BIT6 (CMD)
LSB (CMD)
SDO
POLL STATE
68022 F08
Figure 8. Transmission Format (Poll)
With broadcast commands all devices can be sent commands simultaneously. This is useful for A/D conversion and polling commands. It can also be used with write commands when all parts are being written with the same data. Broadcast read commands should not be used in the parallel configuration. Address Commands: An address command is one in which only the addressed device on the bus responds. The first byte of an address command consists of 4 bits with a value of 1000 and 4 address bits. The second byte is the command byte. See the Bus Protocols and Commands section.
PEC Byte: The packet error code (PEC) byte is a CRC value calculated for all of the bits in a register group in the order they are read, using the following characteristic polynomial: x8 + x2 + x + 1 On a read command, after sending the last byte of a register group, the device will shift out the calculated PEC, MSB first. Toggle Polling: Toggle polling allows a robust determination both of device states and of the integrity of the connections between the devices in a stack. Toggle polling
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is enabled when the LVLPL bit is low. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data out will be low when any device is busy performing an A/D conversion and will toggle at 1kHz when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will toggle at 1kHz when none has an interrupt condition. Toggle Polling--Address Polling: The addressed device drives the SDO line based on its state alone--low for busy/in interrupt, toggling at 1kHz for not busy/not in interrupt. Toggle Polling--Parallel Broadcast Polling: No part address is sent, so all devices respond simultaneously. If a device is busy/in interrupt, it will pull SDO low. If a device is not busy/not in interrupt, then it will release the SDO line (TOS = 0) or attempt to toggle the SDO line at 1kHz (TOS =1). The master controller pulls CSBI high to exit polling. Level polling: Level polling is enabled when the LVLPL bit is high. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data out will be low when any device is busy performing an A/D conversion and will be high when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will be high when none has an interrupt condition. Level polling--Address Polling: The addressed device drives the SDO line based on its state alone--pulled low for busy/in interrupt, released for not busy/not in interrupt. Level polling--Parallel Broadcast Polling: No part address is sent, so all devices respond simultaneously. If a device is busy/in interrupt, it will pull SDO low. If a device is not busy/not in interrupt, then it will release the SDO line. If any device is busy or in interrupt the SDO signal will be low. If all devices are not busy/not in interrupt, the SDO signal will be high. The master controller pulls CSBI high to exit polling. Polling Methods: For A/D conversions, three methods can be used to determine A/D completion. First, a controller can start an A/D conversion and wait for the specified conversion time to pass before reading the results. The second method is to hold CSBI low after an A/D start command has been sent. The A/D conversion status will be output on SDO. A problem with the second method is that the controller is not free to do other serial communication while waiting for A/D conversions to complete. The third method overcomes this limitation. The controller can send an A/D start command, perform other tasks, and then send a Poll A/D Converter Status (PLADC) command to determine the status of the A/D conversions. For OV/UV interrupt status, the poll interrupt status (PLINT) command can be used to quickly determine whether any cell in a stack is in an overvoltage or undervoltage condition. Bus Protocols There are 6 different protocol formats, depicted in Table 3 through Table 8. Table 2 is the key for reading the protocol diagrams.
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Table 2. Protocol Key
PEC N ... Packet error code (CRC-8) Number of bits Continuation of protocol Master-to-slave Slave-to-master Complete byte of data
Table 3. Broadcast Poll Command
8 Command Poll Data
Table 4. Broadcast Read
8 Command 8 Data Byte Low ... 8 Data Byte High 8 PEC
Table 5. Broadcast Write
8 Command 8 Data Byte Low ... 8 Data Byte High
Table 6. Address Poll Command
4 1000 4 Address 8 Command Poll Data
Table 7. Address Read
4 1000 4 Address 8 Command 8 Data Byte Low ... 8 Data Byte High 8 PEC
Table 8. Address Write
4 1000 4 Address 8 Command 8 Data Byte Low ... 8 Data Byte High
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Commands
Table 9. Command Codes
Write Configuration Register Group Read Configuration Register Group Read Cell Voltage Register Group Read Flag Register Group Read Temperature Register Group Start Cell Voltage A/D Conversions and Poll Status WRCFG RDCFG RDCV RDFLG RDTMP STCVAD 0x01 0x02 0x04 0x06 0x08 0x10 (all cell voltage inputs) 0x11 (cell 1 only) 0x12 (cell 2 only) ... 0x1A (cell 10 only) 0x1B (cell 11 only, if CELL10 bit=0) 0x1C (cell 12 only, if CELL10 bit=0) 0x1D (unused) 0x1E (cell self test 1; all CV=0x555) 0x1F (cell self test 2; all CV=0xAAA) 0x20 (all cell voltage inputs) 0x21 (cell 1 only) 0x22 (cell 2 only) ... 0x2A (cell 10 only) 0x2B (cell 11 only, if CELL10 bit=0) 0x2C (cell 12 only, if CELL10 bit=0) 0x2D (unused) 0x2E (cell self test 1; all CV=0x555) 0x2F (cell self test 2; all CV=0xAAA) 0x30 (all temperature inputs) 0x31 (external temp 1 only) 0x32 (external temp 2 only) 0x33 (internal temp only) 0x34--0x3D (unused) 0x3E (temp self test 1; all TMP=0x555) 0x3F (temp self test 2; all TMP=0xAAA) 0x40 0x50 0x60 (all cell voltage inputs) 0x61 (cell 1 only) 0x62 (cell 2 only) ... 0x6A (cell 10 only) 0x6B (cell 11 only, if CELL10 bit=0) 0x6C (cell 12 only, if CELL10 bit=0) 0x6D (unused) 0x6E (cell self test 1; all CV=0x555) 0x6F (cell self test 2; all CV=0xAAA) 0x70 (all cell voltage inputs) 0x71 (cell 1 only) 0x72 (cell 2 only) ... 0x7A (cell 10 only) 0x7B (cell 11 only, if CELL10 bit=0) 0x7C (cell 12 only, if CELL10 bit=0) 0x7D (unused) 0x7E (cell self test 1; all CV=0x555) 0x7F (cell self test 2; all CV=0xAAA)
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Start Open-Wire A/D Conversions and Poll Status
STOWAD
Start Temperature A/D Conversions and Poll Status
STTMPAD
Poll A/D Converter Status Poll Interrupt Status Start Cell Voltage A/D Conversions and Poll Status, with Discharge Permitted
PLADC PLINT STCVDC
Start Open-Wire A/D Conversions and Poll Status, with Discharge Permitted
STOWDC
0
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Memory Map Table 10 through Table 15 show the memory map for the LTC6802-2. Table 15 gives bit descriptions.
Table 10. Configuration (CFG) Register Group
REGISTER CFGR0 CFGR1 CFGR2 CFGR3 CFGR4 CFGR5 RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR BIT 7 WDT DCC8 MC4I MC12I VUV[7] VOV[7] BIT 6 GPIO2 DCC7 MC3I MC11I VUV[6] VOV[6] BIT 5 GPIO1 DCC6 MC2I MC10I VUV[5] VOV[5] BIT 4 LVLPL DCC5 MC1I MC9I VUV[4] VOV[4] BIT 3 CELL10 DCC4 DCC12 MC8I VUV[3] VOV[3] BIT 2 CDC[2] DCC3 DCC11 MC7I VUV[2] VOV[2] BIT 1 CDC[1] DCC2 DCC10 MC6I VUV[1] VOV[1] BIT 0 CDC[0] DCC1 DCC9 MC5I VUV[0] VOV[0]
Table 11. Cell Voltage (CV) Register Group
REGISTER CVR00 CVR01 CVR02 CVR03 CVR04 CVR05 CVR06 CVR07 CVR08 CVR09 CVR10 CVR11 CVR12 CVR13 CVR14 CVR15* CVR16* CVR17* RD/WR RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD BIT 7 C1V[7] C2V[3] C2V[11] C3V[7] C4V[3] C4V[11] C5V[7] C6V[3] C6V[11] C7V[7] C8V[3] C8V[11] C9V[7] C10V[3] C10V[11] C11V[7] C12V[3] C12V[11] BIT 6 C1V[6] C2V[2] C2V[10] C3V[6] C4V[2] C4V[10] C5V[6] C6V[2] C6V[10] C7V[6] C8V[2] C8V[10] C9V[6] C10V[2] C10V[10] C11V[6] C12V[2] C12V[10] BIT 5 C1V[5] C2V[1] C2V[9] C3V[5] C4V[1] C4V[9] C5V[5] C6V[1] C6V[9] C7V[5] C8V[1] C8V[9] C9V[5] C10V[1] C10V[9] C11V[5] C12V[1] C12V[9] BIT 4 C1V[4] C2V[0] C2V[8] C3V[4] C4V[0] C4V[8] C5V[4] C6V[0] C6V[8] C7V[4] C8V[0] C8V[8] C9V[4] C10V[0] C10V[8] C11V[4] C12V[0] C12V[8] BIT 3 C1V[3] C1V[11] C2V[7] C3V[3] C3V[11] C4V[7] C5V[3] C5V[11] C6V[7] C7V[3] C7V[11] C8V[7] C9V[3] C9V[11] C10V[7] C11V[3] C11V[11] C12V[7] BIT 2 C1V[2] C1V[10] C2V[6] C3V[2] C3V[10] C4V[6] C5V[2] C5V[10] C6V[6] C7V[2] C7V[10] C8V[6] C9V[2] C9V[10] C10V[6] C11V[2] C11V[10] C12V[6] BIT 1 C1V[1] C1V[9] C2V[5] C3V[1] C3V[9] C4V[5] C5V[1] C5V[9] C6V[5] C7V[1] C7V[9] C8V[5] C9V[1] C9V[9] C10V[5] C11V[1] C11V[9] C12V[5] BIT 0 C1V[0] C1V[8] C2V[4] C3V[0] C3V[8] C4V[4] C5V[0] C5V[8] C6V[4] C7V[0] C7V[8] C8V[4] C9V[0] C9V[8] C10V[4] C11V[0] C11V[8] C12V[4]
*Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low.
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Table 12. Flag (FLG) Register Group
REGISTER FLGR0 FLGR1 FLGR2 RD/WR RD RD RD BIT 7 C4OV C8OV C12OV* BIT 6 C4UV C8UV C12UV* BIT 5 C3OV C7OV C11OV* BIT 4 C3UV C7UV C11UV* BIT 3 C2OV C6OV C10OV BIT 2 C2UV C6UV C10UV BIT 1 C1OV C5OV C9OV BIT 0 C1UV C5UV C9UV
*Bits C11UV, C12UV, C11OV, and C12OV are always low if the CELL10 bit in register CFGR0 is high.
Table 13. Temperature (TMP) Register Group
REGISTER TMPR0 TMPR1 TMPR2 TMPR3 TMPR4 RD/WR RD RD RD RD RD BIT 7 ETMP1[7] ETMP2[3] ETMP2[11] ITMP[7] REV[2] BIT 6 ETMP1[6] ETMP2[2] ETMP2[10] ITMP[6] REV[1] BIT 5 ETMP1[5] ETMP2[1] ETMP2[9] ITMP[5] REV[0] BIT 4 ETMP1[4] ETMP2[0] ETMP2[8] ITMP[4] THSD BIT 3 ETMP1[3] ETMP1[11] ETMP2[7] ITMP[3] ITMP[11] BIT 2 ETMP1[2] ETMP1[10] ETMP2[6] ITMP[2] ITMP[10] BIT 1 ETMP1[1] ETMP1[9] ETMP2[5] ITMP[1] ITMP[9] BIT 0 ETMP1[0] ETMP1[8] ETMP2[4] ITMP[0] ITMP[8]
Table 14. Packet Error Code (PEC)
REGISTER PEC RD/WR RD BIT 7 PEC[7] BIT 6 PEC[6] BIT 5 PEC[5] BIT 4 PEC[4] BIT 3 PEC[3] BIT 2 PEC[2] BIT 1 PEC[1] BIT 0 PEC[0]
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Table 15. Memory Bit Descriptions
NAME DESCRIPTION VALUES CDC 0 (default) 1 2 CDC Comparator Duty Cycle 3 4 5* 6 7 CELL10 LVLPL GPIO1 GPIO2 WDT DCCx VUV VOV MCxI CxV CxUV CxOV ETMPx THSD REV ITMP PEC 10-Cell Mode Level Polling Mode GPIO1 Pin Control GPIO2 Pin Control Watchdog Timer Discharge Cell x Undervoltage Comparison Voltage* Overvoltage Comparison Voltage* Mask Cell x Interrupts Cell x Voltage* Cell x Undervoltage Flag Cell x Overvoltage Flag External Temperature Measurement* Thermal Shutdown Status Revision Code Internal Temperature Measurement* Packet Error Code UV/OV COMPARATOR PERIOD N/A (Comparator Off) Standby Mode N/A (Comparator Off) 13ms 130ms 500ms 130ms 500ms 2000ms VREF POWERED DOWN BETWEEN MEASUREMENTS Yes No No No No Yes Yes Yes CELL VOLTAGE MEASUREMENT TIME N/A 13ms 13ms 13ms 13ms 21ms 21ms 21ms
*when MMB pin is low, the CDC value is set to 5 0=12-cell mode (default); 1=10-cell mode 0=toggle polling (default); 1=level polling Write: 0=GPIO1 pin pull down on; 1=GPIO1 pin pull down off (default) Read: 0=GPIO1 pin at logic `0'; 1=GPIO1 pin at logic `1' Write: 0=GPIO2 pin pull down on; 1=GPIO2 pin pull down off (default) Read: 0=GPIO2 pin at logic `0'; 1=GPIO2 pin at logic `1' Read Only: 0=WDTB pin at logic `0'; 1=WDTB pin at logic `1' x=1..12 0=turn off shorting switch for cell `x' (default); 1=turn on shorting switch Comparison voltage = VUV * 16 * 1.5mV (default VUV=0. When MMB pin is low a factory programmed comparison voltage is used) Comparison voltage = VOV * 16 * 1.5mV (default VOV=0. When MMB pin is low a factory programmed comparison voltage is used) x=1..12 x=1..12 0=enable interrupts for cell `x' (default) 1=turn off interrupts and clear flags for cell `x' 12-bit ADC measurement value for cell `x' cell voltage for cell `x' = CxV * 1.5mV reads as 0xFFF while A/D conversion in progress cell voltage compared to VUV comparison voltage 0=cell `x' not flagged for under voltage condition; 1=cell `x' flagged cell voltage compared to VOV comparison voltage 0=cell `x' not flagged for over voltage condition; 1=cell `x' flagged
x=1..12 x=1..12
Temperature measurement voltage = ETMPx * 1.5mV 0= thermal shutdown has not occurred; 1=thermal shutdown has occurred Status cleared to `0' on read of Thermal Register Group Device revision code Temperature measurement voltage = ITMP * 1.5mV = 8mV * T(K) CRC value for reads
*Voltage determinations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers.
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LTC6802-2 applicaTions inForMaTion
SERIAL COMMAND Example for LTC6802-2 (Addressable Configuration) Examples below use a configuration of three stacked devices: bottom (B), middle (M), and top (T) Write Configuration Registers (Broadcast Command) 1. 2. 3. 4. Pull CSBI low Send WRCFG command byte Send CFGR0 byte, then CFGR1, CFGR2, ... CFGR5 (All devices on bus receive same data) Pull CSBI high; data latched into all devices on rising edge of CSBI
Calculation of serial interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 command byte and 6 data bytes Serial port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (1+6) * 8 Time for 3 cell stacks example above, with 1MHz serial port = (1/1000000) * (1+6)*8 = 56us Read Cell Voltage Registers (Address Command) 1. 2. 3. 4. 5. 6. Pull CSBI low Send Address byte for bottom device Send RDCV command byte Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), ... CVR17 (B), and then PEC (B) Pull CSBI high Repeat steps 1-5 for middle device and top device
Calculation of serial interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 address, 1 command, 18 register, and 1 PEC byte per device = 21*N Serial port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (21*N) * 8 Time for 3-cell stacks example above, with 1MHz serial port = (1/1000000) * (21*3)*8 = 504us Start Cell Voltage A/D Conversions and Poll Status (Broadcast Command with Toggle Polling) 1. 2. 3. 4. 5. Pull CSBI low Send STCVAD command byte (all devices in stack start A/D conversions simultaneously) SDO output of all devices in parallel pulled low for approximately 12ms SDO output toggles at 1kHz rate, indicating conversions complete for all devices Pull CSBI high to exit polling
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LTC6802-2 applicaTions inForMaTion
Poll Interrupt Status (Level Polling) 1. 2. 3. 4. 5. 6. Pull CSBI low Send Address byte for bottom device Send PLINT command byte SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high Pull CSBI high to exit polling Repeat steps 1-5 for middle device and top device battery system during its useful lifespan. Table 16 shows the various situations that should be considered when planning protection circuitry. The first five scenarios are to be anticipated during production and appropriate protection is included within the LTC6802-2 device itself.
FAULT PROTECTION Overview Care should always be taken when using high energy sources such as batteries. There are numerous ways that systems can be (mis-)configured that might affect a
Table 16. LTC6802-2 Failure Mechanism Effect Analysis
SCENARIO Cell input open circuit (random) Cell input open circuit (random) Top cell input connection loss (V+) Bottom cell input connection loss (V-) EFFECT Power-up sequence at IC inputs Differential input voltage overstress
DESIGN MITIGATION Clamp diodes at each pin to V+ and V- (within IC) provide alternate power path. Zener diodes across each cell voltage input pair (within IC) limits stress.
Power will come from highest connected cell input Clamp diodes at each pin to V+ and V- (within IC) provide or via data port fault current alternate power path. Power will come from lowest connected cell input or via data port fault current Clamp diodes at each pin to V+ and V- (within IC) provide alternate power path. Clamp diodes at each pin to V+ and V- (within IC) provide an alternate power path if there are other devices (which can supply power) connected to the LTC6802-2. The device will enter standby mode within 2 seconds of disconnect. Discharge switches are disabled in standby mode. Use digital isolators to isolate the LTC6802-2 serial port from other LTC6802-2 serial ports. Add parallel Schottky diodes across each cell for load-path redundancy. Diode and connections must handle full operating current of stack, will limit stress on IC Add SCR across each cell for charge-path redundancy. SCR and connections must handle full charging current of stack, will limit stress on IC by selection of trigger Zener
Disconnection of a harness between Loss of supply connection to the IC a group of battery cells and the IC (in a system of stacked groups) Data link disconnection between LTC6802-2 and the master. Cell-pack integrity, break between stacked units Cell-pack integrity, break within stacked unit Cell-pack integrity, break within stacked unit Loss of serial communication (no stress to ICs). No effect during charge or discharge Cell input reverse overstress during discharge
Cell input positive overstress during charge
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LTC6802-2 applicaTions inForMaTion
Internal Protection Diodes Each pin of the LTC6802-2 has protection diodes to help prevent damage to the internal device structures caused by external application of voltages beyond the supply rails as shown in Figure 9. The diodes shown are conventional silicon diodes with a forward breakdown voltage of 0.5V. The unlabeled Zener diode structures have a reverse-breakdown characteristic which initially breaks down at 12V then snaps back to a 7V clamping potential. The Zener diodes labeled ZCLAMP are higher voltage devices with an initial reverse breakdown
V+ LTC6802-2
of 30V snapping back to 25V. The forward voltage drop of all Zeners is 0.5V. Refer to this diagram in the event of unpredictable voltage clamping or current flow. Limiting the current flow at any pin to 10mA will prevent damage to the IC. Cell-Voltage Filtering The LTC6802-2 employs a sampling system to perform its analog-to-digital conversions and provides a conversion result that is essentially an average over the 0.5ms conversion window, provided there isn't noise aliasing with respect to the delta-sigma modulator rate of 512kHz. This indicates that a lowpass filter with useful attenuation at 500kHz may be beneficial. Since the delta-sigma integration bandwidth is about 1kHz, the filter corner need not be lower than this to assure accurate conversions. Series resistors of 100 may be inserted in the input paths without introducing meaningful measurement error, provided only external discharge switch FETs are being used. Shunt capacitors may be added from the cell inputs to V-, creating RC filtering as shown in Figure 10. Note that this filtering is not compatible with use of the internal discharge switches to carry current since this would induce settling errors at the time of conversion as any activated switches temporarily open to provide Kelvin mode cell sensing. As a discharge switch opens, cell wiring resistance will also form a small voltage step (recovery of the small IR drop), so keeping the frequency cutoff of the filter relatively high will allow adequate settling prior to the actual conversion. A guard time of about 60s is provided in the ADC timing, so a 16kHz LP is optimal and offers about 30dB of noise rejection.
Cn 100nF 6.2V Sn 100 Cn - 1 100nF
68021 F10
C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 V
-
ZCLAMP
A3 ZCLAMP A2 A1 A0 CSBI SDO SDI SCKI VMODE ZCLAMP GPIO2 GPIO1 WDTB MMB TOS
68022 F09
100
+
Figure 10. Adding RC Filtering to the Cell Inputs (One Cell Connection Shown)
Figure 9. Internal Protection Diodes
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LTC6802-2 applicaTions inForMaTion
No resistor should be placed in series with the V- pin. Because the supply current flows from the V- pin, any resistance on this pin could generate a significant conversion error for CELL1. READING EXTERNAL TEMPERATURE PROBES Using Dedicated Inputs The LTC6802-2 includes two channels of ADC input, VTEMP1 and VTEMP2, that are intended to monitor thermistors (tempco about -4%/C generally) or diodes (-2.2mV/C typical) located within the cell array. Sensors can be powered directly from VREF as shown in Figure 11 (up to 60A total). For sensors that require higher drive currents, a buffer op amp may be used as shown in Figure 12. Power for the sensor is actually sourced indirectly from the VREG pin
LTC6802-2 VREG VREF VTEMP2 VTEMP1 NC V- 100k 100k
in this case. Probe loads up to about 1mA maximum are supported in this configuration. Since VREF is shutdown during the LTC6802-2 idle and shutdown modes, the thermistor drive is also shut off and thus power dissipation minimized. Since VREG remains always on, the buffer op amp (LT6000 shown) is selected for its ultralow power consumption (10A). Expanding Probe Count The LTC6802-2 provides general purpose I/O pins, GPIO1 and GPIO2, that may be used to control multiplexing of several temperature probes. Using just one of the GPIO pins, the sensor count can double to four as shown in Figure 13. Using both GPIO pins, up to eight sensor inputs can be supported.
LTC6802-2 GPIO1 100k 100k 100k NTC 100k NTC 1F 100k NTC
68022 F13
SN74LVC1G3157 OR SIMILAR DEVICE
VREG VREF VTEMP2 VTEMP1 NC V-
100k
1F 1F
100k NTC 100k NTC
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100k NTC
Figure 11. Driving Thermistors Directly from VREF
Figure 13. Expanding Sensor Count with Multiplexing
Using Diodes to Monitor Temperatures in Multiple Locations
+
LT6000
-
LTC6802-2 VREG VREF VTEMP2 VTEMP1 NC V- 10k 10k
10k NTC 10k NTC
68022 F12
Another method of multiple sensor support is possible without the use of any GPIO pins. If the sensors are PN diodes and several used in parallel, then the hottest diode will produce the lowest forward voltage and effectively establish the input signal to the VTEMP input(s). The hottest diode will therefore dominate the readout from the VTEMP inputs that the diodes are connected to. In this scenario, the specific location or distribution of heat is not known, but such information may not be important in practice. Figure 14 shows the basic concept. In any of the sensor configurations shown, a full-scale cold readout would be an indication of a failed-open sensor connection to the LTC6802-2.
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Figure 12. Buffering VREF for Higher Current Sensors
LTC6802-2 applicaTions inForMaTion
LTC6802-2 VREG VREF VTEMP2 VTEMP1 NC V- 200k 200k
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Figure 14. Using Diode Sensors as Hot-Spot Detectors
ADDING CALIBRATION AND FULL-STACK MEASUREMENTS By adding multiplexing hardware, additional signals can be digitized by the CELL1 ADC channel. One useful signal to provide is a high accuracy voltage reference, such as from an LT(R)1461A-4 or LTC6652A-4.096. By periodic readings of this signal, host software can provide correction of the LTC6802-2 readings to improve the accuracy over that of the internal LTC6802-2 reference, and/or validate ADC operation. Another useful signal is a measure of the
CELL12 2.2M GPIO2 GPIO1 WDTB 1M VREG LTC6802-2 V- C1 150 1F 2N7002 0 = REF_EN 0 = CELL1 1M 1M
total stack potential. This provides a redundant operational measurement of the cells in the event of a malfunction in the normal acquisition process, or as a faster means of monitoring the entire stack potential. Figure 15 shows a means of providing both of these features. A resistor divider is used to provide a low voltage representation of the full stack potential (C12 to C0 voltage) with MOSFETs that decouple the divider current under unneeded conditions. Other MOSFETs, in conjunction with an op amp having a shutdown mode, form a voltage selector that allows measurement of the normal cell1 potential (when GPIO1 is low) or a buffered MUX signal. When the MUX is active (GPIO1 is high), selection can be made between the reference (4.096V) or the full-stack voltage divider (GPOI2 set low will select the reference). During idle time when the LTC6802-2 WDTB signal goes low, the external circuitry goes into a power-down condition, reducing battery drain to a minimum. When not actively performing measurements, GPIO1 should be set low and GPIO2 should be set high to achieve the lowest power state for the configuration shown.
TP0610K 1M VSTACK12 10M LT1461A-4 DNC DNC VIN DNC SD VOUT GND DNC
2N7002 90.9k
4.096V
2.2F
CELL1
TP0610K TP0610K 100 100nF
SD LT1636
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Figure 15. Providing Measurement of Calibration Reference and Full-Stack Voltage Through CELL1 Port
+ -
1M
TP0610K
VDD CH0 CH1 SEL TC4W53FU COM INH VEE VSS
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LTC6802-2 applicaTions inForMaTion
PROVIDING HIGH SPEED OPTO-ISOLATION OF THE SPI DATA PORT Isolation techniques that are capable of supporting the 1Mbps data rate of the LTC6802-2 require more power on the isolated (battery) side than can be furnished by the VREG output of the LTC6802-2. To keep battery drain minimal, this means that a DC/DC function must be implemented along with a suitable data isolation circuit, such as shown in Figure 16. Here an optimal Avago 4-channel (3/1 bidirectional) opto-coupler is used, with a simple isolated supply generated by an LTC1693-2 configured as a 200kHz oscillator. The DC/DC function provides an unregulated logic voltage (~4V) to the opto-coupler isolated side, from energy provided by host-furnished 5V. This circuit provides totally galvanic isolation between the batteries and the host processor, with an insulation rating of 560V continuous, 2500V transient. The Figure 16 functionality is included in the LTC6802-2 demo board. PCB LAYOUT CONSIDERATIONS The VREG and VREF pins should be bypassed with a 1F capacitor for best performance. The LTC6802-2 is capable of operation with as much as 60V between V+ and V-. Care should be taken on the PCB layout to maintain physical separation of traces at different potentials. The pinout of the LTC6802-2 was chosen to facilitate this physical separation. Figure 17 shows the DC voltage on each pin with respect to V- when twelve 3.6V battery cells are connected to the LTC6802-2. There is no more then 5.5V between any two adjacent pins. The package body is used to separate the highest voltage (43.5V) from the lowest voltage (0V).
330 3.57k CSBI SDO SDI 3.57k 3.57k
100k 100k TP0610K 330 TP0610K 330 TP0610K 100k
+5V_HOST CSBI SDI SCKI
SCKI VREG 100nF 249 LTC6802-2 4.99k
SDO
GND_HOST ACSL-6410 ISOLATED VLOGIC BAT54S 1F BAT54S 6* 4 V- VCC1 1F IN1 470pF 20k
*1
3
OUT1 GND1 33nF VCC2 IN2 OUT2 GND2 LTC1693-2 10k
PE68386
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Figure 16. Providing an Isolated High-Speed Data Interface
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LTC6802-2 applicaTions inForMaTion
43.2V 43.2V 43.2V 39.6V 39.6V 36V 36V 32.4V 32.4V 28.8V 28.8V 25.2V 25.2V 21.6V 21.6V 18V 18V 14.4V 14.4V 10.8V 10.8V 7.2V V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 LTC6802-2 CSBI SDO SDI SCKI A3 A2 A1 A0 GPIO2 GPIO1 WDTB MMB TOS VREG VREF VTEMP2 VTEMP1 NC V- S1 C1 S2
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0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 0V TO 5.5V 5.5V 3.1V 1.5V 1.5V 0V 0V 3.6V 3.6V 7.2V
Figure 17. Typical Pin Voltages for 12 3.6V Cells
ADVANTAGES OF DELTA-SIGMA ADCS The LTC6802-2 employs a delta-sigma analog-to-digital converter for voltage measurement. The architecture of delta-sigma converters can vary considerably, but the common characteristic is that the input is sampled many times over the course of a conversion and then filtered or averaged to produce the digital output code. In contrast, a SAR converter takes a single snapshot of the input voltage and then performs the conversion on this single sample. For measurements in a noisy environment, a delta-sigma converter provides distinct advantages over a SAR converter. While SAR converters can have high sample rates, the fullpower bandwidth of a SAR converter is often greater than 1MHz, which means the converter is sensitive to noise out to this frequency. And many SAR converters have much higher bandwidths--up to 50MHz and beyond. It is possible to filter the input, but if the converter is multiplexed
to measure several input channels a separate filter will be required for each channel. A low frequency filter cannot reside between a multiplexer and an ADC and achieve a high scan rate across multiple channels. Another consequence of filtering a SAR ADC is that any noise reduction gained by filtering the input cancels the benefit of having a high sample rate in the first place, since the filter will take many conversion cycles to settle. For a given sample rate, a delta-sigma converter can achieve excellent noise rejection while settling completely in a single conversion--something that a filtered SAR converter cannot do. Noise rejection is particularly important in high voltage switching controllers, where switching noise will invariably be present in the measured voltage. Other advantages of delta sigma converters are that they are inherently monotonic, meaning they have no missing codes, and they have excellent DC specifications.
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LTC6802-2 applicaTions inForMaTion
Converter Details The LTC6802-2's ADC has a second-order delta-sigma modulator followed by a Sinc2, finite impulse response (FIR) digital filter. The front-end sample rate is 512ksps, which greatly reduces input filtering requirements. A simple 16kHz, 1-pole filter composed of a 100 resistor and a 0.1F capacitor at each input will provide adequate filtering for most applications. These component values will not degrade the DC accuracy of the ADC. Each conversion consists of two phases--an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greatly improving CMRR. The second half of the conversion is the actual measurement. Noise Rejection Figure 18 shows the frequency response of the ADC. The roll-off follows a Sinc2 response, with the first notch at 4kHz. Also shown is the response of a 1-pole, 850Hz filter (187s time constant) which has the same integrated response to wideband noise as the LTC6802-2's ADC, which is about 1350Hz. This means that if wideband noise
10 0 -10 -20 -30 -40 -50 -60
is applied to the LTC6802-2 input, the increase in noise seen at the digital output will be the same as an ADC with a wide bandwidth (such as a SAR) preceded by a perfect 1350Hz brickwall lowpass filter. Thus if an analog filter is placed in front of a SAR converter to achieve the same noise rejection as the LTC6802-2 ADC, the SAR will have a slower response to input signals. For example, a step input applied to the input of the 850Hz filter will take 1.55ms to settle to 12 bits of precision, while the LTC6802-2 ADC settles in a single 1ms conversion cycle. This also means that very high sample rates do not provide any additional information because the analog filter limits the frequency response. While higher order active filters may provide some improvement, their complexity makes them impractical for high-channel count measurements as a single filter would be required for each input. Also note that the Sinc2 response has a 2nd order roll-off envelope, providing an additional benefit over a single-pole analog filter.
FILTER GAIN (dB)
10
100
1k 10k FREQUENCY (Hz)
100k
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Figure 18. Noise Filtering of the LTC6802-2 ADC
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LTC6802-2 package DescripTion
(Reference LTC DWG # 05-08-1754 Rev O)
12.50 - 13.10* (.492 - .516) 1.25 0.12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
G Package 44-Lead Plastic SSOP (5.3mm)
7.8 - 8.2
5.3 - 5.7
7.40 - 8.20 (.291 - .323)
0.25 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 - 5.60* (.197 - .221)
0.50 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1.65 - 1.85 (.065 - .073)
0 - 8
2.0 (.079) MAX
PARTING LINE 0.10 - 0.25 (.004 - .010) 0.55 - 0.95** (.022 - .037) 1.25 (.0492) REF
0.50 (.01968) BSC
SEATING PLANE
0.20 - 0.30 (.008 - .012) TYP
0.05 (.002) MIN
G44 SSOP 0607 REV O
NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSIONS ARE IN
MILLIMETERS (INCHES)
4. DRAWING NOT TO SCALE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE **LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
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LTC6802-2 revision hisTory
REV A DATE 01/10 DESCRIPTION Additions to Absolute Maximum Ratings Changes to Electrical Characteristics Change to Graph G10 Text Changes to Pin Functions Replaced Open-Connection Detection Section Edits to Figures 1, 9 Text Changes to Operation Section Text Changes to Applications Information Section Edits to Tables 4, 5, 9, 10, 15, 16 PAGE NUMBER 2 3, 4 5 8, 9 10, 11, 12 11, 26 13 14, 25, 27 19, 20, 21, 23
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6802-2 Typical applicaTion
Stacked Daisy-Chain SPI Bus for LTC6802-2
VBATT
LTC6802-2 IC #3
VREG 1M WDT SDI SCKI CSBI SDO V- 1.8k NDC7002N 2.2k 2.2k 2.2k ALL NPN: CMPT8099 ALL PNP: CMPT8599 ALL PN: RS07J ALL SCHOTTKY: CMD5H2-3
LTC6802-2 IC #2
VREG 100 SDI SCKI CSBI SDO V- 2.2k 2.2k 2.2k
LTC6802-2 IC #1
VREG 100 SDI SCKI CSBI SDO V- 2.2k 2.2k 2.2k
R12 2.2k
68022 TA02
CS CK DI DO
HOST P 500kbps MAX DATA RATE
relaTeD parTs
PART NUMBER LTC6802-1 DESCRIPTION Multicell Battery Stack Monitor with Daisy Chained Serial Interface COMMENTS Functionality equivalent to LTC6802-2, Allows for Multiple Devices to be Daisy Chained
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0110 REV A * PRINTED IN USA
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2009

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